WP5 concerns the integration: a technology level integration of the magnetic layers as a back -end process above the CMOS and a system integration of all the digital and analog functions in a high-end battery-powered wireless IoT platform.
- To analyze the impacts, challenges, and benefits of hybrid CMOS/MRAM design at the system level considering the interplay of digital and analog subsystems in an MRAM-based high-end wireless M2M IoT platform using simulation.
- To demonstrate the manufacturability of CMOS/MSS integrated circuits in an industrial environment
- To validate this approach for multifunctional circuits using the same CMOS/MSS technology by testing the fabricated circuits and comparing their actual performances with the expected ones.
Task 5.1 System integration, simulation and validation (EVADERIS , LIRMM, KIT)
The main objective is to analyze the impact of the Analog/Digital integration into the system and to evaluate the interface between Analog and Digital world particularly with a model of basic embedded system platform for IoT applications (defined with the help of advisory board) using a simulation flow.
Task 5.2 Layout implementation (Tower, CEA, LIRMM, KIT, TUD)
Once the circuits designed, the layout implementation will be carried out at Tower. A shuttle approach (multiproject approach allowing sharing the mask costs between various projects) will be used to minimize the masks costs.
Task 5.3 200mm Hybrid CMOS/MSS wafers (Tower, SING, CEA)
This approach is complementary to T1.4 led by CEA. The 200mm line at TOWER will be used to make industrial demonstration of multifunctional integration using the hybrid CMOS/MSS technology. The stack at wafer level will be deposited on the Singulus tool on 200mm wafers. The final demonstrator will be produced within this task.
Task 5.4 Test of the circuits (CEA, TUD, SING, Tower)
The partners SPINTEC, LIRMM, KIT will receive the circuits that they have designed and will test them. The test results will be compared to the expected performances.