WP2 is dedicated to the design of custom blocks for analog and digital IPs for a typical wireless IoT platform. In particular, we will provide an electrical equivalent compact model of the magnetic devices for electrical simulation, technology files for layout and physical verifications and a library of characterized standard cells for higher level design. Micromagnetic simulations will be performed to make the interface between the technology and the development of the model


  • To develop the compact model of the device
  • To provide a flow for physical verifications (DRC, extraction, LVS…)
  • To design, at circuit level, standard cells to be used for higher level design
Task 2.1: Micromagnetic simulations (UTBV, CEA)

This task will determine by micromagnetic and analytical modelling the static and dynamic behaviors of the free layer magnetization of MTJ under magnetic field and spin-polarized current. Finally, the numerical results will be compared to experimental data from task T1.3.

Task 2.2 Compact model of the device (CEA, LIRMM, TUD, EVADERIS)

This task aims at developing an electrical equivalent compact model of the magnetic devices for electrical simulations.

Task 2.3 Physical verification tools (CEA, EVADERIS)

To draw the masks corresponding to the successive steps of the manufacturing (layout of the circuits), several verification tools are used. In this task, it will be necessary to get the Design Rules (DRs) and the technology parameters from WP1 and integrate them in technology files for these physical verification tools.

Task 2.4 Design of standard cells and simple memory blocks (CEA, LIRMM, KIT, EVADERIS)

The goal of this task will be to design and characterize standard cells based on the hybrid CMOS/Magnetic technology. The availability of such diverse cell library allows us in WP4 to design optimized circuit architectures.