WP1 consists in adapting the properties of the magnetic stack usually used for STT-MTJs to converge to a unique stack allowing performing the memory, RF and sensor functions in the same chip (MSS).


  • To define the composition of the MSS and to grow/optimize its properties on TOWER tool.
  • To demonstrate memory, logic, sensor and RF functions at single cell level using the same stack (MSS).
  • To provide integrated hybrid CMOS/MSS techno at CEA.
  • To provide a first test chip containing elementary IP blocks with MSS and CMOS


Task 1.1: Definition of the Multifunctional Standardized Stack (SING, CEA)

The multifunctional standardized stack (MSS) must allow realizing memory, logic, spin-transfer-oscillator and sensor functionalities without sacrificing on the performances of each function. To achieve this, we intend to adapt standard MTJs.

Task 1.2 : Growth, characterization and optimization of the MSS properties (SING, CEA)

Once defined, the MSS will be grown and optimized on the Singulus deposition tool in collaboration with CEA.

Task 1.3 : Test of the functions at individual cell level (Tower, SING, CEA)

The MSS wafers will then be patterned in nanopillars of different sizes and shapes to test the various foreseen functionalities. The specifications of the MSS in its various functionalities will be provided as inputs for WP2.

Task 1.4: Development of hybrid CMOS/MSS technology (CEA)

The purpose will be to develop this hybrid technology first in the CEA clean room. This task will provide the technology to be used in T5.3 for the circuit fabrication, and to realize a first test chip of a hybrid CMOS/MSS circuit embedding elementary IP blocks for the different functions.