GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way.

Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. The project final objectives are: fabrication of an advanced MSS technology test chip jointly with a system-level simulation and design of a representative M2M IoT platform integrating MSS. The consortium is composed of 9 EU partners led by CEA and of an Advisory Board comprising leaders in IP solutions, IoT, and mobile technologies.

 

Strategic objectives addressed:

  • Demonstrate the relevance of the magnetic Multifunctional Standardized Stack in a CMOS process for the co-integration of digital, analog and RF IPs using Spin Transfer Torque devices.
  • Investigate, design, develop, and analyze hybrid MRAM-CMOS digital building blocks, architecture and subsystem for energy-constraint high-performance embedded system applications and IoT, particularly smart communication systems to show systemability of the technology.
  • Implement an advanced MSS test chip to show integrability and manufacturability of this low power, highly integrated technology into three strategic markets: telecommunication, IoT & security.