- Scientific publications
Leveraging Systematic Unidirectional Error-Detecting Codes for Fast STT-MRAM Cache
N. Sayed, F. Oboril, R. Bishnoi, and M. B. Tahoori, in proceedings of VLSI Test Symposium (VTS), 2017, USA.
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Opportunistic Write for Fast and Reliable STT-MRAM
N. Sayed, M. Ebrahimi, R. Bishnoi, and M. B. Tahoori, in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.
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VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories
S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, and M. B. Tahoori, in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland
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D2.2 - Consolidated verilogA model
This deliverable consists in developing a compact model of the MSS device based on a perpendicular STT-MTJ required for electrical simulations.
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D2.3 - Magnetic technology files
In D2.3, CEA has developed all the necessary tools allowing the design of hybrid CMOS/MSS circuits using standards methods/CAD tools and covering all the design steps.
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Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices
Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié
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Design of Defect and Fault Tolerant Non-Volatile Spintronic Flip-Flops
R. Bishnoi, F. Oboril and M.B. Tahoori, "Design of Defect and Fault Tolerant Non-Volatile Spintronic Flip-Flops", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017.
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D6.9 - GREAT web site
Spintec & Toplink Innovation have worked on the development of a public web site dedicated to the project.
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