Last week (November 9th), the project first review meeting in Brussels was the opportunity for Spintec & GREAT partners to expose to the Commission their first achievements after 9 months at multiple levels : management, scientific, and also more industrial outcomes such as the project 1st foundry tape out.
Indeed, the first demonstrator of the GREAT project has been submitted to Tower on November 2016. This hybrid integrated circuit uses the 180nm CMOS process from Tower and an academic MRAM post-process that will be done by Spintec Lab within their facilities. This demonstrator embeds several different functional blocks, all based on Multifunctional Standardized Stack Magnetic Tunnel Junctions: some are dedicated to RF applications, some use specific non-volatile digital cells and others are more dedicated to magnetic sensors. These different blocks will be electrically tested and the complete hybrid CMOS/MRAM process will be characterized in the same time. Results are expected Q2-2017.
GREAT consortium is still in line with initial objectives and EC conclusions are very good. The project made a satisfactory projection towards the milestones and deliverables.
- The management of the project works well (good communication and a good operation of the task forces),
- The Multifunctional Standardized Stack technology and the associated process for the first demonstrator have been defined,
- The tools have been provided allowing the designers to integrate not only test structures, but also relatively simple circuits in the first demonstrator,
- A full design flow was set up for system level investigations and digital implementation of circuits, opening the way to the implementation of the second demonstrator and simulation of a representative application.